Various kinds of analog-digital converters have been used in accordance with required accuracy and transformation speed FIG. 1 shows a conventional analog-digital converter of a parallel-comparison type for example, which is disclosed in Japanese Laid-Open Patent No. 58-69112.
The A/D converter of FIG. 1 converts analog input signals to digital signals of four bits comprising a sum of the most significant two bits and the least significant two bits. The analog input signals are sample-held by a sample-hold circuit 11, and are respectively input to three comparators 12a, 12b and 12c disposed in parallel with each other. Primary reference voltages at predetermined levels are provided for the respective comparators 12a, 12b and 12c, and are generated by a reference voltage generator 13 comprising four resistors 13a, 13b, 13c and 13d connected in series to each other. The analog input signals are respectively compared in voltage level with the primary reference voltages in the comparators 12a, 12b and 12c. The comparators 12a, 12b and 12c respectively output "1" as the compared results when the analog input voltages are greater than and equal to the respective primary reference voltages, and output "0" in the other case.
These outputs are supplied to exclusive logical sum circuits(EX-ORs) 14a, 14b, 14c and 14d disposed in parallel with each other, and are logically processed in them. The respective logical outputs of these EX-ORs 14a, 14b, 14c and 14d are supplied to an encoder 15 and are encoded therein to obtain digital signals of the most significant two bits in the analog input signals.
The primary reference voltages V.sub.ref, V.sub.11, V.sub.10, V.sub.01, and V.sub.00 generated in the reference voltage generator 13 are supplied to switching circuits 16a, 16b, 16c and 16d selectively controlled by the outputs of the EX-ORs. These switching circuits 16a, 16b, 16c and 16d supply the primary reference voltages most close to the levels of the analog input signals with respect to the primary reference voltages V.sub.ref, V.sub.10, and V.sub.00 in the odd sequential order, to one terminal of a potential divider 17 constituted by four resistors 17a, 17b, 17c and 17d connected in series to each other. These switching circuits also supply to the other terminal of the potential divider 17 the primary reference voltages most close to the levels of the analog input signals with respect to the primary reference voltages V.sub.11 and V.sub.01 in the even sequential order.
The potential divider 17 equally divides the supplied primary reference voltages and generates secondary reference voltages V.sub.11, V.sub.10, and V.sub.01, and supplies the secondary reference voltages to the comparators 18a, 18b and 18c to which the analog input signals are input. The comparators 18a, 18b and 18c compare the voltage levels of the analog input signals and the secondary reference voltages. The compared results by the respective comparators 18a, 18b and 18c are supplied to the encoder 20 through a switching circuit 19, and are encoded therein to obtain digital signals of the least significant two bits in the analog input signals.
The switching of the switching circuit 19 is controlled by an OR circuit 21 for logically summing the outputs of EX-ORs 14a and 14c to inverse the bit sequential order in the outputs of the comparators 18a, 18b and 18c. The high and low levels of the secondary reference voltages supplied to the potential divider 17 are inverted in accordance with the levels of the analog input signals so that the compared results are inverted with respect to the secondary reference voltages The inverse operation of the switching circuit 19 is performed to compensate the inverted compared results. Such a switching circuit 19 may be constituted by a plurality of pair transistors for performing the switch operation by switching electrical current paths as shown in FIG. 2.
As mentioned above, the compared results of the respective comparators 18a, 18b and 18c are inverted by the switching circuit 19 to compensate the inversion of the high and low levels of the secondary reference voltages supplied to the potential divider 17, and are supplied to the encoder 20.
Accordingly, the number of switches constituting the switching circuit 19 are increased as the increase of the number of comparators for comparing the analog input signals and the secondary reference voltages When the number of bits on the least significant bit side representing resolution ability in the digital signals is n, it is necessary to dispose (2.sup.n -2) switches. Therefore, the number of switches constituting the switching circuit 19 is exponentially increased as the increase of the resolution ability. Further, it is necessary to dispose {2.times.(2.sup.n -2)+1}wirings for connecting from the comparators for comparing the analog input signals and the secondary reference voltages to the switches constituting the switching circuit 19. Accordingly, the number of wirings also is exponentially increased as the increase of the resolution ability.
These problems result in the increases of the number of elements and wiring regions .when an A/D converter is integrated, and are hindrances to high integration in the A/D converter having high resolution ability.